This invention relates generally to semiconductor device packages, and in particular to semiconductor die flip chip packages. More specifically, the invention relates to structures and assembly procedures for low stress thin die flip chip packages suited for low-K Si dice and/or thin core substrates.
In semiconductor device package assembly, a semiconductor die (also referred to as an integrated circuit (IC) chip or “chip”) may be bonded directly to a package substrate. Such die is formed with bumps of solder affixed to its I/O bonding pads. During conventional packaging assembly, the die is “flipped” onto its front surface (e.g., active circuit surface) so that the solder bumps form electrical and mechanical connections directly between the die and conductive metal pads on the package substrate. Underfill is then applied between the gap formed by the solder bumps in order to further secure the die to the package substrate. Next, a stiffener made of substantially copper is placed around the die and attached to the package substrate. Lastly, a heat spreader is attached over the die and the stiffener. A semiconductor device package of this type is commonly called a “semiconductor die flip chip package.”
A problem with such a semiconductor die flip chip package is that it is subject to different temperatures during the packaging process. For instance, different temperatures arise with the cool down from the solder joining temperature and the underfill curing temperature. As a result, the package is highly stressed due to the different coefficients of thermal expansion (CTE) of the various package and die materials. The high stress experienced by bonded materials during cooling may cause them to warp or crack and cause the package structure to bow, thereby, adversely affecting the board level reliability of the package. In some cases, the bow of the package will exceed the co-planarity specification for the semiconductor die flip chip package.
As the semiconductor industry seeks to improve the performances of semiconductor die flip chip packages, there is a drive towards using low-K Si dice (including extra-low-K Si dice) and/or thin package substrates (in particular thin core or coreless package substrates) in semiconductor die flip chip packages. However, as compared to traditional dielectric materials in conventional silicon based dice, the low-K dielectric materials in low-K Si dice are brittle and tend to crack under substantially less stress. As such, it is possible for the reliability of a low-K Si die to be compromised due to cracking of the low-K dielectric material. In addition, thin package substrates allow the transfer of stress to become more direct between components coupled to the thin package substrates. As such, the CTE mismatches between the die, bumps, underfill, package substrate, and BGA balls can cause earlier failures in a semiconductor die flip chip package during board level reliability tests.
Accordingly, what is needed are semiconductor die flip chip packages and corresponding assembly methods that can incorporate low-K Si dice and/or thin package substrates such that their board level reliabilities and/or their package warpages (e.g., co-planarity) can come within acceptable limits for incorporation into electronic devices.